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CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TO 5
User’s Manual U15905EJ2V1UD
257
8.4.7
Square-wave output operation (16-bit resolution)
The V850ES/SA2 and V850ES/SA3 are provided with a 16-bit register that can be used only during cascade
connection.
The 16-bit resolution timer/event counter mode is selected by setting the TMC34 and TCM54 bits of 8-bit timer
mode control registers 3 and 5 (TMC3 and TMC5) to 1.
8-bit timer/event counter n outputs a square wave of any frequency using the interval preset in 16-bit timer
compare registers 23 and 45 (CR23 and CR45).
In the following description, TM2 and TM3 are used. Read TM2 and TM3 as TM4 and TM5 when using TM4 and
TM5.
Setting method (when TM2 and TM3 are connected in cascade)
<1>
Set each register.
TCL2 register:
TCL2 selects the count clock (t)
(The TCL3 register does not have to be set in cascade connection)
CR2 register:
Compare value (N) ... Lower 8 bits (settable from 00H to FFH)
CR3 register:
Compare value (N) ... Higher 8 bits (settable from 00H to FFH)
TMC2, TCM3 registers: Stops count operation, selects the mode in which clear & start occurs on a
match between the TM23 register and CR23 register.
LVS2
LVR2
Timer Output F/F Status Settings
1
0
High-level output
0
1
Low-level output
Enables timer output F/F inversion, and enables timer output.
TMC2 register = 00001011B or 00000111B
TMC3 register = 00010000B
<2>
Set the TMCE3 bit of the TMC3 register to 1. Then set the TMCE2 bit of the TMC2 register to 1 to start
the count operation.
<3>
When the values of the TM23 register and the CR23 register connected in cascade match, the TO2 timer
output F/F is inverted. Moreover, INTTM2 is generated and the TM23 register is cleared to 0000H.
<4>
Then, the timer F/F is inverted during the same interval and a square wave is output from the TO2 pin.
Frequency = 1/2t (N + 1): N = 0000H to FFFFH
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